Methods for Forming Nickel Oxide Films for Use With Resistive Switching Memory Devices

ABSTRACT

Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH) 2  film on the substrate, where the forming the Ni(OH) 2  occurs at the cathode; and annealing the Ni(OH) 2  film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH) 2  film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material such as: Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, a Ni alloy, a Pt alloy, an Ir alloy, a Ti alloy, an Al alloy, a Cu alloy, a Co alloy, a Ru alloy, and an Rh alloy.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional claiming priority to U.S. patentapplication Ser. No. 11/963,656 filed on Dec. 21, 2007, now issued asU.S. Pat. No. 8,283,214, which is incorporated herein by reference inits entirety for all purposes.

BACKGROUND

Non-volatile memory devices based on the resistivity switching oftransition-metal oxide materials has become a major focus for developingthe next generation universal RAM devices. As may be appreciated,non-volatile memory does not require a constant power supply to retainstored information in contrast to volatile memory, which does require aconstant power supply to retain stored information. Thus, non-volatilememory may have advantages for long term storage of critical data.

Many types of materials have been utilized to create non-volatile memoryelements. Nickel oxide thin films are one such material. Conventionally,nickel oxide thin films have been prepared through physical-vapordeposition (PVD) methods by reactive sputtering of Ni targets in an O₂enriched environment. In addition, in some examples, conventionalmethods have generated reproducible resistance switching in anappropriate metal-insulator (NiO thin film)-metal structure withsuperior performances both in terms of reliability and speed.

Research of nickel oxide thin films has demonstrated that the defectchemistry of those films can play a role in determining the switchingperformance of the associated memory devices derived from those films.For example, according to some research, the atomic elemental ratiobetween nickel and oxygen must be carefully controlled to within certainranges to obtain a desired resistance switching. Current depositiontechniques may not provide sufficiently precise control over chemicaldefects in oxide materials.

As such, methods for forming nickel oxide films for use with resistiveswitching memory devices are presented herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1A is an illustrative perspective representation of a resistiveswitching memory element in accordance with embodiments of the presentinvention;

FIG. 1B is an illustrative cross-sectional representation of a resistiveswitching memory element in accordance with embodiments of the presentinvention;

FIG. 2A is an illustrative perspective representation of a resistiveswitching memory element in accordance with embodiments of the presentinvention;

FIG. 2B is an illustrative cross-sectional representation of a resistiveswitching memory element in accordance with embodiments of the presentinvention;

FIG. 3 is an illustrative flowchart for methods for forming a resistiveswitching memory element on a substrate in accordance with embodimentsof the present invention;

FIGS. 4A-B are illustrative representations of a build-up for aresistive switching memory element utilizing methods described herein inaccordance with embodiments of the present invention; and

FIG. 5 is an illustrative graphical representation of a ramp anneal inaccordance with embodiments of the present invention.

DETAILED DESCRIPTION

The present invention will now be described in detail with reference toa few embodiments thereof as illustrated in the accompanying drawings.In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one skilled in the art, that the presentinvention may be practiced without some or all of these specificdetails. In other instances, well known process steps and/or structureshave not been described in detail in order to not unnecessarily obscurethe present invention.

The illustrative examples presented herein are for clarifyingembodiments of the present invention. Theses illustrations are not scalerepresentations of embodiments and should not be construed as solimiting with respect to scale and proportion. In addition, theillustrations provided may, in some examples, represent only a portionof an integrated memory device for clarity. Thus, substrates, dielectricmaterials, conductive materials, semiconductor features, semiconductordevices, or other associated elements or devices may be specificallyexcluded for the sole purpose of presenting simplified embodiments.

Non-volatile memory devices based on the resistivity switching oftransition-metal oxide materials has been a major focus for developingthe next generation universal RAM devices. NiO-based oxide thin filmsprepared from physical-vapor deposition (PVD) methods by reactivesputtering of Ni targets in O₂-containing environments have beendemonstrated to be able to generate reproducible resistance switching inan appropriate metal-insulator (NiO thin film)-metal structure. Further,it has been established that the defect chemistry of NiO may play a rolein determining the switching performance of NiO thin films. Inparticular, the atomic elemental ratio between Ni and O can becontrolled within certain ranges to obtain the resistance switching.However, in some implementations PVD exhibits poor control over thechemical defects in oxide materials. In addition, PVD can be anexpensive deposition method due to the complexity of the PVD equipmentand associated consumable parts. Therefore, low-cost chemical depositionmethods that can generate NiO films with well-controlled chemical defectlevels for the non-volatile memory application may be desirable.

FIG. 1A is an illustrative perspective representation of a resistiveswitching memory device 100 in accordance with embodiments of thepresent invention. As illustrated, NiO film 104 is disposed on electrode106. Electrode 106 provides a first conductive element for resistiveswitching memory element 100. In some embodiments, NiO films may beelectrochemically deposited on electrodes utilizing methods providedherein. Electrode 102 provides a second conductive element for resistiveswitching memory element 100. In some embodiments, electrodes may beformed from Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, and their alloys. Inaddition, in some embodiments, NiO film 104 may include a dopant oralloying element such as Co, Li, Mg, and Cr. Dopants, as may beappreciated, may be selected to provide specific and desired switchingcharacteristics for a memory device.

It may be appreciated that electrodes 102 and 106 may be formed in anymanner well-known in the art without departing from the presentinvention including: PVD, CVD, ALD, ECP, and Electroless depositiontechniques. In general, memory device 100 forms a memory element equalto one bit. The memory element may have a value of 0 or 1 depending onthe resistance across the element. For example, when the resistanceacross the element is high (e.g., 10 kOhm), the element has a value of0, and when the resistance is low (e.g., 1 kOhm), the element has avalue of 1. The resistance of the element can be changed by changing theresistance of the NiO film 104, which can be changed by applying avoltage across the element (e.g., one voltage to change to a 0, andanother voltage to change to 1). The element's value (i.e., resistance)may be determined by using a read voltage that does not disturb thestate of the element.

FIG. 1B, which corresponds with FIG. 1A, is an illustrativecross-sectional representation of a resistive switching memory element120 in accordance with embodiments of the present invention. As above,resistive switching memory element 120 includes electrode 106, NiO film104, and electrode 102. In some embodiments, a buffer layer (not shown)may be formed on NiO film 104 to provide adhesion enhancement and adiffusion barrier.

FIG. 2A is an illustrative perspective representation of a resistiveswitching memory element in accordance with embodiments of the presentinvention. As illustrated, NiO film 204 is disposed on electrode 206.Electrode 206 provides a first conductive element for resistiveswitching memory element 200. In some embodiments, NiO films may beelectrochemically deposited on electrodes utilizing methods providedherein. Electrode 202 provides a second conductive element for resistiveswitching memory element 200. In some embodiments, electrodes may beformed from Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, and their alloys. Inaddition, in some embodiments, NiO film 204 may include a dopant oralloying element such as Co, Li, Mg, and Cr. Dopants, as may beappreciated, may be selected to provide specific and desired switchingcharacteristics for a memory device. It may be appreciated thatelectrodes 202 and 206 may be formed in any manner well-known in the artwithout departing from the present invention including: PVD, CVD, ALD,ECP, and electroless deposition techniques. In addition, in someembodiments, resistive memory element 200 may further include currentsteering element 208, which may include a diode, a resistor, or atransistor. FIG. 2B, which corresponds with FIG. 2A, is an illustrativecross-sectional representation of a resistive switching memory element220 in accordance with embodiments of the present invention. As above,resistive switching memory element 220 includes electrode 206, NiO film204, electrode 202, and current steering element 208. In someembodiments, a buffer layer (not shown) may be formed on NiO film 204 toprovide adhesion enhancement and a diffusion barrier.

FIG. 3 is an illustrative flowchart 300 for methods for forming aresistive switching memory element on a substrate in accordance withembodiments of the present invention. At a first step 302, a Ni²⁺ ionsolution is prepared. In embodiments described herein, an appropriateNi²⁺ ion solution may be prepared from a Ni(NO₃)₂ solution having aconcentration in the range of approximately 10 mM to 2M and having anadjusted solution pH in the range of approximately 1.0 to 5.0. In someembodiments, a Ni(NO₃)₂ solution may be more preferably prepared havinga concentration in the range of approximately 0.1M to 1M and having anadjusted solution pH in the range of approximately 3.0 to 4.0. As may beappreciated, Ni(NO₃)₂ solutions may be prepared in any manner well-knownin the art without departing from the present invention. In addition, insome embodiments, a dopant such as Co, Li, Mg, and Cr, may be added to aNi(NO₃)₂ solution without limitation. In some embodiments, dopants maybe present as nitrate salts in the form of Co(NO₃)₂, LiNO₃, Mg(NO₃)₂,and Cr(NO₃)₃ having a concentration range of approximately 1.0 mM to0.1M.

At a next step 304, a substrate is received. A substrate may be receivedby any configuration capable of performing wet processes withoutdeparting from the present invention. As such, in embodiments, asubstrate may be immersed in a bath, or may be sprayed in some fashion.Notably, a substrate may include a bottom electrode that may be utilizedas a cathode for a subsequent electrochemical deposition step. Referringbriefly to FIG. 4A, FIG. 4A is an illustrative representation of abuild-up for a resistive switching memory element utilizing methodsdescribed herein in accordance with embodiments of the presentinvention. Thus, a substrate may include a bottom electrode 402 asillustrated. Returning to FIG. 3, at a next step 306, the methoddetermines whether to pre-treat the substrate. A substrate may bepre-treated to enhance adhesion of subsequent layers. If the methoddetermines at a step 306 not to pre-treat the substrate, the methodcontinues to a step 310 to form a Ni(OH)₂ film on the substrate. If themethod determines at a step 306 to pre-treat the substrate, the methodcontinues to a step 308 to pre-treat the substrate. In some embodiments,pre-treating may include a chemical cleaning or an electrochemicalcleaning. Thus, in some embodiments, a chemical cleaning may beperformed that includes washing the substrate in an H₂SO₄ solution for30 to 120 seconds (s), where the H₂SO₄ solution has a concentration inthe range of 0.5 to 2.0 M, and where the solution is maintained at roomtemperature. In some embodiments, a chemical cleaning may be performedthat includes washing the substrate in an H₂SO₄ and HNO₃ solution for 10to 60 s, where the H₂SO₄ and HNO₃ solution has an H₂SO₄ concentration of0.5 to 2.0 M and an HNO₃ concentration in a range of 0.1 to 1.0 M, andwhere the solution is maintained at room temperature.

In some embodiments, an electrochemical cleaning may be performed thatincludes performing an in-situ cathodic reduction in a deposition bathat a potential of −0.4 to −0.7 volts (V) vs. Ag/AgCl (sat. KCl) for 10to 60 s. In some embodiments, an electrochemical cleaning may beperformed that includes performing a cathodic reduction in an H₂SO₄solution at a potential of approximately −0.4 to −0.7V vs. Ag/AgCl (sat.KCl) for 10 to 60 s where the H₂SO₄ solution has a concentration of 0.1to 1.0 M. As may be appreciated, selection of a chemical cleaning or anelectrochemical cleaning may be made on the basis of compatiblechemistries without departing from the present invention.

At a next step 310, the method continues to form a Ni(OH)₂ film on asubstrate. In some embodiments, a Ni(OH)₂ film may be formed on asubstrate by electrochemically depositing the film on the substrate. Asnoted above, a substrate may include a bottom electrode that may beutilized as a cathode for a subsequent electrochemical deposition step.Referring briefly to FIG. 4A, a bottom electrode 402 is illustratedhaving a Ni(OH)₂ film 404 formed thereon. As may be appreciated,electrochemical deposition requires an anode, which, in someembodiments, is formed from a conductive material such as Ni, Pt, a Nialloy, and a Pt alloy. In some embodiments, an electrochemicaldeposition process proceeds under a set of operational parameters thatincludes: a current density in a range of approximately 50.0 1-A/cm² to2.0 mA/cm²; a peak current of approximately 0.1 to 1.0 mA/cm², the peakcurrent including a current on/off time ratio in a range ofapproximately 1:10 to 10:1; and a current scan range of approximately0.05 to 2.00 mA/cm². In some embodiments, the set of operationalparameters more preferably includes: a current density of approximately0.1 to 0.5 mA/cm²; and a current scan range of approximately 50.01-A/cm² to 0.5 mA/cm².

In other embodiments, an electrochemical deposition may further includeutilizing a reference electrode for use with a potential controlwaveform. In some embodiments, a potential control waveform proceedsunder a set of operational parameters including: an applied potentialselected to induce a current flow of approximately 50.0 1-A/cm² to 2.0mA/cm²; and a potential scan range selected to induce a current flow ofapproximately 0.05 to 2.00 mA/cm². In some embodiments, the set ofoperational parameters more preferably includes: an applied potentialselected to induce a current flow of approximately 0.1 to 0.5 mA/cm².Furthermore, in some embodiments, the reference electrode may include: ahydrogen reference electrode, an Ag/AgCl reference electrode, and a Ptwire pseudo reference electrode. The method then continues to anneal theNi(OH)₂ film.

In some embodiments, co-depositing other materials utilizing techniquesdescribed above may be performed. For example, in one embodiment, a Cosalt may be co-deposited to form a mixed layer of Co(OH)₂/Ni(OH)₂. Themixed layer of Co(OH)₂ /Ni(OH)₂ may then be annealed to form a mixedcobalt oxide and nickel oxide layer. Other mixtures are possible as wellwithout departing from the present invention.

An anneal process may be utilized to convert the Ni(OH)₂ film to an NiOfilm by thermal decomposition of the Ni(OH)₂ film 406 as illustrated inFIG. 4A. Two types of annealing may be favorably utilized in embodimentsdisclosed herein: ramp annealing and constant annealing. Returning toFIG. 3, at a next step 312, the method determines whether to perform aramp anneal. If the method determines at a step 312 to perform a rampanneal, the method continues to a step 314 to perform a ramp anneal of aNi(OH)₂ film formed on a substrate. Referring briefly to FIG. 5, FIG. 5is an illustrative graphical representation 500 of a ramp anneal inaccordance with embodiments of the present invention. In someembodiments, a ramp anneal may be performed in four segments. In a firstsegment 502, the ramp anneal is performed at a temperature ofapproximately 250 to 350° C. with a ramp rate of approximately 0.1 to20° C. /sec and a holding temperature of approximately 350° C. forapproximately 30 to 300 s. In a second segment 504, the ramp anneal isperformed at a temperature of approximately 350 to 450 ° C. with a ramprate of approximately 0.1 to 20° C./sec and a holding temperature ofapproximately 450° C. for approximately 30 to 300 s. In a third segment506, the ramp anneal is performed at a temperature of approximately 450to 600° C. with a ramp rate of approximately 0.1 to 20° C./sec and aholding temperature of approximately 600° C. for approximately 30 to 300s. In a fourth segment 508, the ramp anneal is performed at atemperature of approximately 600 to 800° C. with a ramp rate ofapproximately 0.1 to 20° C./sec and a holding temperature ofapproximately 800° C. for approximately 30 to 300 s.

Returning to FIG. 3, if the method determines at a step 312 not toperform a ramp anneal, the method continues to a step 316 to perform aconstant anneal. In some embodiments, a constant anneal is performed ata temperature of approximately 250 to 800° C. for approximately 10 to600 s. In some embodiments, methods may include combinations of a rampanneal and a constant anneal. Thus, in one embodiments, a ramp annealmay be performed followed by a constant anneal. In another embodiment, aconstant anneal may be performed followed by a ramp anneal. After themethod completes conversion of the Ni(OH)₂ film to an NiO film bythermal decomposition (i.e. annealing), the method ends.

FIG. 4B is an illustrative representation of a build-up for a resistiveswitching memory element utilizing methods described herein inaccordance with embodiments of the present invention. As noted above forFIG. 3, bottom electrode 402 may be utilized as a cathode for anelectrochemical deposition of a Ni(OH)₂ film. A Ni(OH)₂ film may then beconverted to NiO film 406 by thermal decomposition. In some embodiments,top electrode 408 may then be formed upon NiO film 406. Top electrodesmay be formed on a NiO film in any manner well-known in the art withoutdeparting from the present invention. In some embodiments, electrodesmay be formed from Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, and their alloys.It may be appreciated that electrodes 402 and 408 may be formed in anymanner well-known in the art without departing from the presentinvention including: PVD, CVD, ALD, ECP, and Electroless depositiontechniques. In addition, in some embodiments, Ni0 film 406 may include adopant or alloying element such as Co, Li, Mg, and Cr. Dopants, as maybe appreciated, may be selected to provide specific and desiredswitching characteristics for a memory device. In some embodiments,buffer layer 410 may be formed on top electrode 408 to provide adhesionenhancement and diffusion barrier. As above, buffer layers may be formedon top electrodes in any manner well-known in the art without departingfrom the present invention.

While this invention has been described in terms of several embodiments,there are alterations, permutations, and equivalents, which fall withinthe scope of this invention. It should also be noted that there are manyalternative ways of implementing the methods and apparatuses of thepresent invention. Furthermore, unless explicitly stated, any methodembodiments described herein are not constrained to a particular orderor sequence. Further, the Abstract is provided herein for convenienceand should not be employed to construe or limit the overall invention,which is expressed in the claims. It is therefore intended that thefollowing appended claims be interpreted as including all suchalterations, permutations, and equivalents as fall within the truespirit and scope of the present invention.

What is claimed is:
 1. A resistive switching memory element, comprising:a first conductive layer; a nickel oxide layer formed on the firstconductive layer; and a second conductive layer formed above the nickeloxide layer; wherein the first and second conductive layers are operableas electrodes; wherein a resistance of the nickel oxide layer isswitchable between two different values by applying a voltage across theelectrodes; and wherein the nickel oxide layer is formed byelectrochemical deposition.
 2. The resistive switching memory element ofclaim 1, wherein the first conductive layer comprises at least one ofnickel, platinum, iridium, titanium, aluminum, copper, cobalt,ruthenium, rhenium, or their alloys.
 3. The resistive switching memoryelement of claim 1, wherein the first conductive layer is formed by atleast one of physical vapor deposition, chemical vapor deposition,atomic layer deposition, electrochemical plating, or electrolessdeposition.
 4. The resistive switching memory element of claim 1,wherein the nickel oxide layer is formed by electrochemical depositionusing the first conductive layer as a cathode.
 5. The resistiveswitching memory element of claim 4, wherein the first conductive layeris chemically or electrochemically cleaned before the nickel oxide layeris formed.
 6. The resistive switching memory element of claim 1, whereinthe nickel oxide layer is deposited as Ni(OH)₂ and converted to NiO bythermal decomposition.
 7. The resistive switching memory element ofclaim 6, wherein the thermal decomposition results from annealing at atemperature between 250 and 800 C.
 8. The resistive switching memoryelement of claim 1, wherein the nickel oxide layer is formed byelectrochemical deposition from a Ni(NO₃)₂ solution.
 9. The resistiveswitching memory element of claim 8, wherein the Ni(NO₃)₂ solutionfurther comprises an additional nitrate salt.
 10. The resistiveswitching memory element of claim 9, wherein the additional nitrate saltcomprises at least one of Co(NO₃)₂, LiNO₃, Mg(NO₃)₂, or Cr(NO₃)₃. 11.The resistive switching memory element of claim 10, wherein theCo(NO₃)₂, LiNO₃, Mg(NO₃)₂, or Cr(NO₃)₃ is co-deposited with the Ni(NO₃)₂to form a mixed layer of Co(OH)₂/Ni(OH)₂, LiNO₃/Ni(OH)₂,Mg(NO₃)₂/Ni(OH)₂, or Cr(NO₃)₃/Ni(OH)₂.
 12. The resistive switchingmemory element of claim 11, wherein the mixed layer is converted to amixed oxide layer by thermal decomposition.
 13. The resistive switchingmemory element of claim 12, wherein the thermal decomposition resultsfrom annealing at a temperature between 250 and 800 C.
 14. The resistiveswitching memory element of claim 1, wherein the nickel oxide layerfurther comprises at least one dopant or at least one alloying element.15. The resistive switching memory element of claim 1, wherein thenickel oxide layer further comprises at least one of cobalt, lithium,magnesium, or chromium.
 16. The resistive switching memory element ofclaim 1, further comprising a buffer layer between the nickel oxidelayer and the second conductive layer.
 17. The resistive switchingmemory element of claim 16, wherein the buffer layer is operable toenhance adhesion.
 18. The resistive switching memory element of claim16, wherein the buffer layer is operable as a diffusion barrier.
 19. Theresistive switching memory element of claim 1, wherein the secondconductive layer comprises at least one of nickel, platinum, iridium,titanium, aluminum, copper, cobalt, ruthenium, rhenium, or their alloys.20. The resistive switching memory element of claim 1, wherein thesecond conductive layer is formed by at least one of physical vapordeposition, chemical vapor deposition, atomic layer deposition,electrochemical plating, or electroless deposition.